The present invention relates, in general, to vertical field effect transistors. More particularly, the invention relates to self-aligned vertical field effect transistors having an improved source contact area.
Vertical field effect transistors, also called double diffused MOSFETs (DMOS) are well known. These devices include a p-type base region and an n-type source region diffused through a single window defined by an edge of a polysilicon gate. The source region is completely contained within the base region, so that a portion of both the source and base regions extends beneath the gate. A channel region is thus formed beneath the gate between the lateral boundaries of the source region and the base region. To improve performance, a source electrode must be made to contact both the source region and the base region. Performance is further improved by doping the portion of the base region underneath the source contact more heavily than the channel region.
Cost of manufacture of vertical field effect transistors is proportional to size of the transistor, number of mask steps required to produce the transistor, and overall yield of good devices. One method of reducing the number of mask steps required is to use a self-aligned process, whereby elements of the transistor are defined by deposition, diffusion, and etching processes but not by photoresist alignment processes. An advantage of the self-aligned process is that all critical elements are aligned to the polysilicon gate without mask registration error, which reduces yield loss due to misalignment. Self-aligned manufacturing processes lower cost by reducing the labor and overhead associated with the alignment processes, and by allowing smaller dimensions, resulting in smaller size of the transistor.
A previous self-aligned vertical field effect transistor process was described by Mutsuhio Mori et al. in "An insulated gate bipolar transistor with a self-aligned DMOS structure", IEDM 88-813, 1988. In this structure, a phosphosilicate oxide sidewall spacer was used to form the n-type source region and to isolate the gate from the source electrode. The n-type source region diffused laterally from the edges of the phosphosilicate oxide sidewall spacer, diffusing on one side beneath the gate to define the channel region, and diffusing on the other side to create a contact area for the source contact. The phosphosilicate oxide served also to isolate the source electrode from the polysilicon gate.
To fabricate a low on-resistance vertical field effect transistor it is important that the contact between the source electrode and the source region be a low resistance contact. Contact resistance is a function of contact area between the source region and the source electrode and doping density of the source region. Previous self-aligned processes such as the process described in the Mori et al. article, defined the contact area completely by the lateral diffusion of dopant from the phosphosilicate oxide, as described above. This lateral diffusion was often too small to make a low resistance ohmic contact. One possible solution to this problem was to increase the size of the source region, which had the undesired effect of increasing size of the transistor. Another solution was to isotropically etch the phosphosilicate oxide to expose more of the underlying source region, but due to the high dopant concentration of the phosphosilicate oxide controlled isotropic etching was difficult. Thus, a process for manufacturing self-aligned vertical field effect transistors with an improved contact area between the source region and the source electrode is needed.
To obtain a high source doping density, the phosphosilicate oxide must contain a high concentration of phosphorous. Also, aluminum electrodes are usually used to make electrical contact to the source region. It is known, however, that corrosion results when aluminum electrodes are placed in contact with oxides having a high concentration of phosphorous. In order to improve the reliability of the transistor, the phosphosilicate oxide must not contact the source electrode.
Accordingly, it is an object of the present invention to provide an improved method for manufacturing a self-aligned vertical field effect transistor.
It is a further object of the present invention to provide a self-aligned vertical field effect transistor with improved yield.
It is a further object of the present invention to provide an improved self-aligned vertical field effect transistor which is lower in cost.
It is a further object of the present invention to provide an improved self-aligned vertical field effect transistor with improved reliability.
It is still a further object of the present invention to provide a self-aligned vertical field effect transistor with improved process control.